View ISL12028_292394.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL12028
New Features
Data Sheet
April 17, 2006
FN8233.3
Real Time Clock/Calendar with EEPROM
The ISL12028 device is a low power real time clock with clock/calender, power-fail indicator, clock output and crystal compensation, two periodic or polled alarms (CMOS output), intelligent battery backup switching, CPU Supervisor, integrated 512 x 8 bit EEPROM configured in 16 Byte per page. The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes, and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction.
Features
* Real Time Clock/Calendar - Tracks time in Hours, Minutes, and Seconds - Day of the Week, Day, Month, and Year - 3 Selectable Frequency Outputs * Two Non-Volatile Alarms - Settable on the Second, Minute, Hour, Day of the Week, Day, or Month - Repeat Mode (periodic interrupts) * Automatic Backup to Battery or SuperCap - Power Failure Detection - 800nA Battery Supply Current * On-Chip Oscillator Compensation - Internal Feedback Resistor and Compensation Capacitors - 64 Position Digitally Controlled Trim Capacitor - 6 Digital Frequency Adjustment Settings to 30ppm * 512 x 8 Bits of EEPROM: - 16-Byte Page Write Mode (32 total pages) - 8 Modes of Block LockTM Protection - Single Byte Write Capability - Data Retention: 50 years - Endurance: >2,000,000 Cycles Per Byte * CPU Supervisor Functions: - Power On Reset, Low Voltage Sense - Watchdog Timer (0.25, 0.75, 1.75 sec) * I2C* Interface - 400kHz Data Transfer Rate * 14 Ld SOIC and TSSOP Packages * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
14 LD TSSOP/SOIC
X1 X2 NC NC NC RESET GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD VBAT FOUT/IRQ NC NC SCL SDA
NC = No internal connection
Applications
* * * * * * * * * * * * * * 1 Utility Meters HVAC Equipment Audio/Video Components Modems Network Routers, Hubs, Switches, Bridges Cellular Infrastructure Equipment Fixed Broadband Wireless Equipment Pagers/PDA POS Equipment Test Meters/Fixtures Office Automation (Copiers, Fax) Home Appliances Computer Products Other Industrial/Medical/Automotive
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. *I2C is a Trademark of Philips. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL12028 Ordering Information
PART NUMBER (Note) ISL12028IB27Z ISL12028IB27AZ ISL12028IB30AZ ISL12028IBZ ISL12028IBAZ ISL12028IV27Z ISL12028IV27AZ ISL12028IV30AZ ISL12028IVZ ISL12028IVAZ PART MARKING 12028IB27Z 12028IB27AZ 12028IB30AZ 12928IBZ 12028IBAZ 12028IV27Z 1202827AZ 1202830AZ 12028IVZ 12028IVAZ VRESET VOLTAGE 2.63V 2.92V 3.09V 4.38V 4.64V 2.63V 2.92V 3.09V 4.38V 4.64V TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-free) 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP PKG. DWG. # M14.15 M14.15 M14.15 M14.15 M14.15 M14.173 M14.173 M14.173 M14.173 M14.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Tape & Reel - add "-T" suffix after the part number.
Block Diagram
OSC Compensation
X1
32.768kHz
X2
Oscillator
Frequency Divider
1Hz
Timer Calendar Logic
Time Keeping Registers (SRAM)
Battery Switch Circuitry
VDD VBACK
IRQ/FOUT
Select Status Registers (SRAM) Mask
SCL SDA
Serial Interface Decoder
Control Decode Logic
Control/ Registers (EEPROM)
Alarm
Compare Alarm Regs (EEPROM) 4K EEPROM ARRAY
8
RESET
Watchdog Timer Low Voltage Reset
2
FN8233.3 April 17, 2006
ISL12028 Pin Descriptions
PIN NUMBER 1 2 6 SYMBOL X1 X2 RESET DESCRIPTION The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. RESET. This is a reset signal output. This signal notifies a host processor that the "watchdog" time period has expired or that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended value for the pull-up resistor is 5k, If unused, connect to ground. Ground. Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR'ed with other open drain or open collector outputs. The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the configuration register. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. Power Supply. No Internal Connection.
7 8 9 12 13 14 3, 4, 5, 10, 11
GND SDA SCL
IRQ/FOUT
VBAT VDD N.C.
3
FN8233.3 April 17, 2006
ISL12028
Absolute Maximum Ratings
Voltage on VDD, VBAT, SCL, SDA, RESET and IRQ/FOUT Pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on X1 and X2 Pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V ESD Rating (MIL-STD-883, Method 3014) . . . . . . . . . . . . . . .>2kV ESD Rating (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . .>175V
Thermal Information
Thermal Resistance (Note) JA (C/W) 14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 100 14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 110 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Operating Characteristics
Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40C to +85C, Typical values are at TA = 25C and VDD = 3.3V SYMBOL VDD VBAT PARAMETER Main Power Supply Backup Power Supply CONDITIONS MIN 2.7 1.8 TYP MAX 5.5 5.5 UNIT V V NOTES
Electrical Specifications
SYMBOL IDD1 PARAMETER Supply Current with I2C Active CONDITIONS VDD = 2.7V VDD = 5.5V IDD2 Supply Current for Non-Volatile Programming Supply Current for Main Timekeeping (Low Power Mode) Battery Supply Current VDD = 2.7V VDD = 5.5V VDD = VSDA = VSCL = 2.7V VDD = VSDA = VSCL = 5.5V VBAT = 1.8V, VDD = VSDA = VSCL = VRESET = 0V VBAT = 3.0V, VDD = VSDA = VSCL = VRESET = 0V IBATLKG VTRIP VTRIPHYS VBATHYS VDD SRBattery Input Leakage VBAT Mode Threshold VTRIP Hysteresis VBAT Hysteresis VDD Negative Slew Rate VDD = 5.5V, VBAT = 1.8V 1.8 2.2 30 50 10 800 850 MIN TYP MAX 500 800 2.5 3.5 10 20 1000 1200 100 2.6 UNIT A A mA mA A A nA nA nA V mV mV V/ms 5 5, 7 5, 7 6 1, 4, 5 1, 2, 3 NOTES 1, 2, 3
,3
3
IDD3
IBAT
IRQ/FOUT, RESET OUTPUTS VOL Output Low Voltage VDD = 5.5V IOL = 3mA VDD = 2.7V IOL = 1mA RESET OUTPUT ILO Output Leakage Current VDD = 5.5V VOUT = 5.5V 100 400 nA 0.3*VDD 0.3*VDD V V
IRQ/FOUT, OUTPUT VOH Output High Voltage VDD = 5.5V IOL = -1.0mA VDD = 2.7V IOL = -0.4mA VDD x 0.7 VDD x 0.7 V V
4
FN8233.3 April 17, 2006
ISL12028
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL tRPD tPURST VRVALID VRESET PARAMETER VDD Detect to RESET LOW Power Up Reset Time-Out Delay Minimum VDD for Valid RESET Output ISL12028-4.5A Reset Voltage Level ISL12028 Reset Voltage Level ISL12028-3 Reset Voltage Level ISL12028-2.7A Reset Voltage Level ISL12028-2.7 Reset Voltage Level tWDO Watchdog Timer Period 32.768kHz crystal between X1 and X2 100 1.0 4.59 4.33 3.04 2.87 2.58 1.70 725 225 tRST tRSP Watchdog Timer Reset Time-Out Delay I2C Interface Minimum Restart Time 32.768kHz crystal between X1 and X2 225 1.2 4.64 4.38 3.09 2.92 2.63 1.75 750 250 250 4.69 4.43 3.14 2.97 2.68 1.801 775 275 275 CONDITIONS MIN TYP (Note 5) 500 250 400 MAX UNITS ns ms V V V V V V s ms ms ms s NOTES 7
EEPROM SPECIFICATIONS EEPROM Endurance EEPROM Retention Temperature 75C >2,000,000 50 Cycles Years
Serial Interface (I2C) Specifications
SYMBOL VIL VIH PARAMETER SDA, and SCL Input Buffer LOW Voltage SDA, and SCL Input Buffer HIGH Voltage CONDITIONS SBIB = 1 (Under VDD mode) SBIB = 1 (Under VDD mode) SBIB = 1 (Under VDD mode) IOL = 4mA VIN = 5.5V VIN = 5.5V MIN -0.3 0.7 x VDD 0.05 x VDD 0 0.1 0.1 0.4 10 10 TYP MAX 0.3 x VDD VDD + 0.3 UNITS V V V V A A NOTES
Hysteresis SDA and SCL Input Buffer Hysteresis VOL ILI ILO SDA Output Buffer LOW Voltage Input Leakage Current on SCL I/O Leakage Current on SDA
TIMING CHARACTERISTICS fSCL tIN tAA SCL Frequency Pulse width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Time the bus must be free before the start of a new transmission Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 400 50 900 kHz ns ns
tBUF
ns
5
FN8233.3 April 17, 2006
ISL12028
Serial Interface (I2C) Specifications (Continued)
SYMBOL tLOW tHIGH tSU:STA tHD:STA PARAMETER Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time CONDITIONS Measured at the 30% of VDD crossing. Measured at the 70% of VDD crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VDD. From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD From SCL falling edge crossing 70% of VDD to SDA entering the 30% to 70% of VDD window. From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. From 30% to 70% of VDD From 70% to 30% of VDD MIN 1300 600 600 600 TYP MAX UNITS ns ns ns ns NOTES
tSU:DAT
Input Data Setup Time
100
ns
tHD:DAT
Input Data Hold Time
0
ns
tSU:STO
STOP Condition Setup Time
600
ns
tHD:STO tDH
STOP Condition Hold Time for Read, or Volatile Only Write Output Data Hold Time
600 0
ns ns
tR tF Cb Cpin tWC NOTES:
SDA and SCL Rise Time SDA and SCL Fall Time
20 + 0.1 x Cb 20 + 0.1 x Cb 10
250 250 400 10 12 20
ns ns pF pF ms 8
Capacitive Loading of SDA or SCL Total on-chip and off-chip SDA, and SCL Pin Capacitance Non-volatile Write Cycle Time
1. IRQ/FOUT Inactive (no frequency output and no alarms). 2. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz. 3. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V. 4. Bit BSW = 0 (Standard Mode), VBAT 1.8V. 5. Specified at 25C. 6. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 7. Parameter is not 100% tested. 8. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
6
FN8233.3 April 17, 2006
ISL12028 Timing Diagrams
tF tHIGH tLOW tR tHD:STO
SCL tSU:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tHD:STA
tAA SDA (OUTPUT TIMING)
tDH
tBUF
FIGURE 1. BUS TIMING
SCL
SDA
8TH BIT OF LAST BYTE
ACK tWC STOP CONDITION START CONDITION
FIGURE 2. WRITE CYCLE TIMING
tRSP tRSPtWDO tRST
tRSP>tWDO tRST
SCL
SDA
RESET START STOP START
Note: All inputs are ignored during the active reset period (tRST). FIGURE 3. WATCHDOG TIMING
VRESET VDD tPURST tRPD tR RESET tF VRVALID tPURST
FIGURE 4. RESET TIMING
7
FN8233.3 April 17, 2006
ISL12028 Typical Performance Curves
4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 1.8
Temperature is 25C unless otherwise specified
0.90 0.80
BSW = 0 or 1
0.70
SCL,SDA pullups = 0V
0.60 0.50 0.40 0.30
SCL,SDA pullups = 0V BSW = 0 or 1
Ibat (uA)
SCL,SDA pullups = Vbat BSW = 0 or 1
2.3 2.8 3.3 3.8 4.3 4.8 5.3
Ibat
0.20 0.10 0.00 1.80
2.30
2.80
3.30
3.80
4.30
4.80
5.30
Vbat (V)
Vbat(V)
FIGURE 5. IBAT vs VBAT, SBIB = 0
FIGURE 6. IBAT vs VBAT, SBIB = 1
5.00 4.50 4.00 3.50
1.40
Vdd=5.5V
1.20
Vbat = 3.0V
1.00
2.50 2.00 1.50 1.00
Ibat (uA)
Idd (uA)
3.00
Vdd=3.3V
0.80
0.60
0.40
0.20 0.50 0.00 -45 0.00 -45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature
Temperature
FIGURE 7. IDD3 vs TEMPERATURE
FIGURE 8. IBAT vs TEMPERATURE
4.50 4.00 3.50 3.00
80
60
PPM change from ATR=0
40
Idd (uA)
2.50 2.00 1.50 1.00 0.50 0.00 1.8
20
0
-20
2.3
2.8
3.3
3.8
4.3
4.8
5.3
-40 -32 -28 -24 -20 -16 -12
-8
-4
0
4
8
12
16
20
24
28
Vdd (V)
ATR setting
FIGURE 9. IDD3 vs VDD
FIGURE 10. FOUT vs ATR SETTING
8
FN8233.3 April 17, 2006
ISL12028 Description
The ISL12028 device is a Real Time Clock with clock/ calendar, two polled alarms with integrated 512x8 EEPROM, oscillator compensation, CPU Supervisor (Power on Reset, Low Voltage Sensing and Watchdog Timer) and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost. The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction. The Dual Alarms can be set to any Clock/Calendar value for a match. For instance, every minute, every Tuesday, or 5:23 AM on March 21. The alarms can be polled in the Status Register or can provide a hardware interrupt (IRQ/FOUT Pin). There is a repeat mode for the alarms allowing a periodic interrupt. The IRQ/FOUTpin may be software selected to provide a frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive. The ISL12028 device integrates CPU Supervisory functions (POR, WDT) and Battery Switch. There is Power-On-Reset (RESET) output with 250ms delay from power on when the VDD supply crosses the VRESET threshold for the device. It will also assert RESET when VDD goes below the specified VRESET threshold for the device. The VRESET threshold is selectable via VTS2/VTS1/VTS0 registers to five (5) preselected levels. There is WatchDog Timer (WDT) with 3 selectable time-out periods (0.25s, 0.75s and 1.75s) and disabled setting. The WatchDog Timer activates the RESET pin when it expires. Normally, the I2C Interface is disabled when the RESET output is active, but this can be changed by using a register bit to enable I2C operation in battery backup mode. The device offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or SuperCap. The entire ISL12028 device is fully operational from 2.7 to 5.5V and the clock/calendar portion of the ISL12028 device remains fully operational down to 1.8V (Standby Mode). The ISL12028 device provides 4k bits of EEPROM with 8 modes of BlockLockTM control. The BlockLock allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area. gated). The pull-up resistor on this pin must use the same voltage source as VDD.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated). This open drain output requires the use of a pull-up resistor. The pull-up resistor on this pin must use the same voltage source as VDD. The output circuitry controls the fall time of the output signal with the use of a slope controlled pulldown. The circuit is designed for 400kHz I2C interface speed.
VBAT
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event the VDD supply fails. This pin can be connected to a battery, a SuperCap or tied to ground if not used.
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency out control bits of the control/status register. * Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output. * Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open drain output.
RESET
The RESET signal output can be used to notify a host processor that the watchdog timer has expired or the VDD voltage supply has dipped below the VRESET threshold. It is an open drain, active LOW output. Recommended value for the pullup resistor is 10k. If unused it can be tied to ground.
X1, X2
The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL12028 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40C to +85C. This oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and microcontroller for active compensation. X2 is intended to drive a crystal only, and should not drive any external circuit.
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not
9
FN8233.3 April 17, 2006
ISL12028
NO EXTERNAL COMPENSATION RESISTORS OR CAPACITORS ARE NEEDED OR ARE RECOMMENDED TO BE CONNECTED TO THE X1 AND X2 PINS. temperature dependent, the RTC performance will also be dependent upon temperature. The frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystal's nominal frequency. For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil's RTC family provides onchip crystal compensation networks to adjust loadcapacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information see the Application section.
X1 X2
FIGURE 11. RECOMMENDED CRYSTAL CONNECTION
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representation of the second, minute, hour, day, date, month, and year. The RTC has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the ISL12028 powers up after the loss of both VDD and VBAT, the clock will not operate until at least one byte is written to the clock register.
Clock/Control Registers (CCR)
The Control/Clock Registers are located in an area separate from the EEPROM array and are only accessible following a slave byte of "1101111x" and reads or writes to addresses [0000h:003Fh]. The clock/control memory map has memory addresses from 0000h to 003Fh. The defined addresses are described in the Table 2. Writing to and reading from the undefined addresses are not recommended.
Reading the Real Time Clock
The RTC is read by initiating a Read command and specifying the address corresponding to the register of the Real Time Clock. The RTC Registers can then be read in a Sequential Read Mode. Since the clock runs continuously and read takes a finite amount of time, there is a possibility that the clock could change during the course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continuous to run. Alarms occurring during a read are unaffected by the read operation.
CCR Access
The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a three step process (See section "Writing to the Clock/Control Registers.") The CCR is divided into 5 sections. These are: 1. Alarm 0 (8 bytes; non-volatile) 2. Alarm 1 (8 bytes; non-volatile) 3. Control (5 bytes; non-volatile) 4. Real Time Clock (8 bytes; volatile) 5. Status (1 byte; volatile) Each register is read and written through buffers. The nonvolatile portion (or the counter portion of the RTC) is updated only if RWEL is set and only after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another section requires a new operation. A read or write can begin at any address in the CCR. It is not necessary to set the RWEL bit prior to writing the status register. Section 5 (status register) supports a single byte read or write only. Continued reads or writes from this section terminates the operation. The state of the CCR can be read by performing a random read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the
Writing to the Real Time Clock
The time and date may be set by writing to the RTC registers. RTC Register should be written ONLY with Page Write. To avoid changing the current time by an uncompleted write operation, write to the all 8 bytes in one write operation. When writing the RTC registers, the new time value is loaded into a separate buffer at the falling edge of the clock during the Acknowledge. This new RTC value is loaded into the RTC Register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and the contents of the buffer are discarded. After a valid write operation the RTC will reflect the newly loaded data beginning with the next "one second" clock cycle after the stop bit is written. The RTC continues to update the time while an RTC register write is in progress and the RTC continues to run during any non-volatile write sequences.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the accuracy of the quartz crystal that is used as the time base for the RTC. Since the resonant frequency of a crystal is
10
FN8233.3 April 17, 2006
ISL12028
clock does not change the time being read. A sequential read of the CCR will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next Register.
BAT: Battery Supply
This bit set to "1" indicates that the device is operating from VBAT, not VDD. It is a read-only bit and is set/reset by hardware (ISL12028 internally). Once the device begins operating from VDD, the device sets this bit to "0".
AL1, AL0: Alarm Bits
These bits announce if either alarm 0 or alarm 1 match the real time clock. If there is a match, the respective bit is set to `1'. The falling edge of the last data bit in a SR Read operation resets the flags. Note: Only the AL bits that are set when an SR read starts will be reset. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete.
Real Time Clock Registers (Volatile)
SC, MN, HR, DT, MO, YR: Clock/Calendar Registers
These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
OSCF: Oscillator Fail Indicator
This bit is set to "1" if the oscillator is not operating. The bit is set to "0" only if the oscillator is functioning. This bit is read only, and is set/reset by hardware.
DW: Date of the Week Register
This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-12-... The assignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software designer. The default value is defined as `0'.
RWEL: Register Write Enable Latch
This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to "1" prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence.
Y2K: Year 2000 Register
Can have value 19 or 20. As of the date of the introduction of this device, there would be no real use for the value 19 in a true real time clock, however.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12-hour format and H21 bit functions as an AM/PM indicator with a `1', representing PM. The clock defaults to standard time with H21 = 0.
WEL: Write Enable Latch
The WEL bit controls the access to the CCR during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR address will be ignored, although acknowledgment is still issued. The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a "0" to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition.
Leap Years
Leap years add the day February 29 and are defined as those years that are divisible by 4.
Status Register (SR) (Volatile)
The Status Register is located in the CCR memory map at address 003Fh. This is a volatile register only and is used to control the WEL and RWEL write enable latches, read power status and two alarm bits. This register is separate from both the array and the Clock/Control Registers (CCR).
TABLE 1. STATUS REGISTER (SR) ADDR 003Fh Default 7 BAT 0 6 AL1 0 5 4 3 0 0 2 RWEL 0 1 WEL 0 0 RTCF 1
RTCF: Real Time Clock Fail Bit
This bit is set to a "1" after a total power failure. This is a read only bit that is set by hardware (ISL12028 internally) when the device powers up after having lost all power to the device (both VDD and VBAT go to 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to "1". On power up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte is written to the clock register. The first valid write to the RTC section after a complete power failure resets the RTCF bit to "0" (writing one byte is sufficient).
AL0 OSCF 0 0
11
FN8233.3 April 17, 2006
ISL12028
TABLE 2. CLOCK/CONTROL MEMORY MAP (Shaded cells indicate that NO other value is to be written to that bit. X indicates the bits are set according to the product variation, see device ordering information) DEFAULT 01h 19/20 0-6 0-99 1-12 1-31 0-23 0-59 0-59 20h 00h 00h 01h 00h 00h 00h 00h 4Xh 00h 00h 00h 18h 19/20 0-6 1-12 1-31 0-23 0-59 0-59 19/20 0-6 1-12 1-31 0-23 0-59 0-59 20h 00h 00h 00h 00h 00h 00h 20h 00h 00h 00h 00h 00h 00h BIT ADDR. 003F 0037 0036 0035 0034 0033 0032 0031 0030 0014 0013 0012 0011 0010 000F 000E 000D 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 Alarm0 (EEPROM) Alarm1 (EEPROM) Control (EEPROM) TYPE Status RTC (SRAM) REG NAME SR Y2K DW YR MO DT HR MN SC PWR DTR ATR INT BL Y2K1 DWA1 YRA1 MOA1 DTA1 HRA1 MNA1 SCA1 Y2K0 DWA0 YRA0 MOA0 DTA0 HRA0 MNA0 SCA0 EMO0 EDT0 EHR0 EMN0 ESC0 EMO1 EDT1 EHR1 EMN1 ESC1 0 EDW0 7 BAT 0 0 Y23 0 0 MIL 0 0 SBIB 0 0 IM BP2 0 EDW1 6 AL1 0 0 Y22 0 0 0 M22 S22 BSW 0 0 AL1E BP1 0 0 0 0 0 A1M22 A1S22 0 0 0 0 0 A0M22 A0S22 5 AL0 Y2K21 0 Y21 0 D21 H21 M21 S21 0 0 ATR5 AL0E BP0 A1Y2K21 0 0 A1D21 A1H21 A1M21 A1S21 A0Y2K21 0 0 A0D21 A0H21 A0M21 A0S21 4 OSCF Y2K20 0 Y20 G20 D20 H20 M20 S20 0 0 ATR4 FO1 WD1 A1Y2K20 0 A1G20 A1D20 A1H20 A1M20 A1S20 A0Y2K20 0 A0G20 A0D20 A0H20 A0M20 A0S20 3 0 Y2K13 0 Y13 G13 D13 H13 M13 S13 0 0 ATR3 FO0 WD0 A1Y2K13 0 A1G13 A1D13 A1H13 A1M13 A1S13 A0Y2K13 0 A0G13 A0D13 A0H13 A0M13 A0S13 2 RWEL 0 DY2 Y12 G12 D12 H12 M12 S12 VTS2 DTR2 ATR2 0 0 0 DY2 A1G12 A1D12 A1H12 A1M12 A1S12 0 DY2 A0G12 A0D12 A0H12 A0M12 A0S12 1 WEL 0 DY1 Y11 G11 D11 H11 M11 S11 VTS1 DTR1 ATR1 0 0 0 DY1 A1G11 A1D11 A1H11 A1M11 A1S11 0 DY1 A0G11 A0D11 A0H11 A0M11 A0S11 0 RTCF Y2K10 DY0 Y10 G10 D10 H10 M10 S10 VTS0 DTR0 ATR0 0 0 A1Y2K10 DY0 A1G10 A1D10 A1H10 A1M10 A1S10 A0Y2K10 DY0 A0G10 A0D10 A0H10 A0M10 A0S10 RANGE
Unused - Default = RTC Year value (No EEPROM) - Future expansion
Unused - Default = RTC Year value (No EEPROM) - Future expansion
Unused Bits:
Bit 3 in the SR is not used, but must be zero. The Data Byte output during a SR read will contain a zero in this bit location.
Alarm Registers (Non-Volatile)
Addresses 0Ch to 0Fh
The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = "1"). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. See the Device Operation and Application section for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described under this section are non-volatile.
12
FN8233.3 April 17, 2006
ISL12028 BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. The partitions are described in Table 3.
TABLE 3. PROTECTED ADDRESSES ISL12028 None (Default) 180h - 1FFh 100h - 1FFh 000h - 1FFh 000h - 03Fh 000h - 07Fh 000h - 0FFh 000h - 1FFh BP2 BP1 BP0 ARRAY LOCK None Upper 1/4 Upper 1/2 Full Array First 4 Pages First 8 Pages First 16 Pages Full Array TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS FO1 0 0 1 1 FO0 0 1 0 1 OUTPUT FREQUENCY Alarm output (FOUT disabled) 32.768kHz 4096Hz 1Hz
Oscillator Compensation Registers
There are two trimming options. - ATR. Analog Trimming Register - DTR. Digital Trimming Register These registers are non-volatile. The combination of analog and digital trimming can give up to -64 to +110 ppm of total adjustment.
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1, ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the RTC. Each bit has a different weight for capacitance adjustment. For example, using a Citizen CFS-206 crystal with different ATR bit combinations provides an estimated ppm adjustment range from -34 to +80ppm to the nominal frequency compensation.
INT Register: Interrupt Control and Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically enable or disable the alarm interrupt signal output (IRQ/ FOUT). The interrupts are enabled when either the AL1E or AL0E or both bits are set to `1' and both the FO1 and FO0 bits are set to 0 (FOUT disabled). The IM bit enables the pulsed interrupt mode. To enter this mode, the AL0E or AL1E bits are set to "1", and the IM bit to "1". The IRQ/FOUT output will now be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. In the case both Alarms are enabled.
X1
CX1
CRYSTAL OSCILLATOR
X2
CX2
FIGURE 12. DIAGRAM OF ATR
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three divisions of the internal oscillator, that is applied to the IRQ/ FOUT output pin. Table 4 shows the selection bits for this output. When using this function, the Alarm output function is disabled.
The effective on-chip series load capacitance, CLOAD, ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default). CLOAD is changed via two digitally controlled capacitors, CX1 and CX2, connected from the X1 and X2 pins to ground (see Figure 12). The value of CX1 and CX2 is given by the following formula:
C X = ( 16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 )pF
The effective series load capacitance is the combination of CX1 and CX2:
C LOAD = ---------------------------------X1 X2
1 1 1 ---------- + ---------- C C
16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9 C LOAD = ---------------------------------------------------------------------------------------------------------------------------- pF
2
13
FN8233.3 April 17, 2006
ISL12028
For example, CLOAD(ATR = 00000) = 12.5pF, CLOAD(ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111) = 20.25pF. The entire range for the series combination of load capacitance goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values.
VTS2, VTS1, VTS0: VRESET Select Bits
The ISL12028 is shipped with a default VDD threshold (VRESET) per the ordering information table. This register is a non-volatile with no protection, therefore any writes to this location can change the default value from that marked on the package. If not changed with a non-volatile write, this value will not change over normal operating and storage conditions. However, ISL12028 has four (4) additional selectable levels to fit the customers application. Levels are: 4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. The VRESET selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 6 below.
TABLE 6. VTS2 0 0 0 0 1 VTS1 0 0 1 1 0 VTS0 0 1 0 1 0 VRESET 4.64V 4.38V 3.09V 2.92V 2.63V
DTR Register - DTR2, DTR1, DTR0: Digital Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the number of counts per second and average the ppm error to achieve better accuracy. DTR2 is a sign bit. DTR2 = 0 means frequency compensation is > 0. DTR2 = 1 means frequency compensation is < 0. DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm adjustment and DTR0 gives 20 ppm adjustment. A range from -30ppm to +30ppm can be represented by using three bits above.
TABLE 5. DIGITAL TRIMMING REGISTERS DTR REGISTER DTR2 0 0 0 0 1 1 1 1 DTR1 0 1 0 1 0 1 0 1 DTR0 0 0 1 1 0 0 1 1 ESTIMATED FREQUENCY PPM 0 +10 +20 +30 0 -10 -20 -30
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers requires the following steps: 1. Write a 02h to the Status Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). 2. Write a 06h to the Status Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). Write all eight bytes to the RTC registers, or one byte to the SR, or one to five bytes to the control registers. This sequence starts with a start bit, requires a slave byte of "11011110" and an address within the CCR and is terminated by a stop bit. A write to the EEPROM registers in the CCR will initiate a non-volatile write cycle and will take up to 20ms to complete. A write to the RTC registers (SRAM) will require much shorter cycle time (t = tBUF). Writes to undefined areas have no effect. The RWEL bit is reset by the completion of a write to the CCR, so the sequence must be repeated to again initiate another change to the CCR contents. If the sequence is not completed for any reason (by sending an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. Writing all zeros to the status register resets both the WEL and RWEL bits. A read operation occurring between any of the previous operations will not interrupt the register write operation.
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0 SBIB: - Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by setting this bit to "1". This will minimize power drain on the battery. The Serial Interface can be enabled in battery backup mode by setting this bit to "0". (default is "0"). See Reset and Power Control section.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for switching between VDD and Back Up Battery. There are two options. Option 1. Standard Mode: Set "BSW = 0" Option 2. Legacy/Default Mode: Set "BSW = 1" See Power Control Operation later in this document for more details. Also see "I2C Communications During Battery backup and LVR Operation" in the Applications section for important details.
14
FN8233.3 April 17, 2006
ISL12028
Alarm Operation
Since the alarm works as a comparison between the alarm registers and the RTC registers, it is ideal for notifying a host processor of a particular time event and trigger some action as a result. The host can be notified by either a hardware interrupt (the IRQ/FOUT pin) or by polling the Status Register (SR) Alarm bits. These two volatile bits (AL1 for Alarm 1 and AL0 for Alarm 0), indicate if an alarm has happened. The bits are set on an alarm condition regardless of whether the IRQ/ FOUT interrupt is enabled. The AL1 and AL0 bits in the status register are reset by the falling edge of the eighth clock of status register read. There are two alarm operation modes: Single Event and periodic Interrupt Mode: 1. Single Event Mode is enabled by setting the AL0E or AL1E bit to "1", the IM bit to "0", and disabling the frequency output. This mode permits a one-time match between the alarm registers and the RTC registers. Once this match occurs, the AL0 or AL1 bit is set to "1" and the IRQ/FOUT output will be pulled low and will remain low until the AL0 or AL1 bit is read, which will automatically resets it. Both Alarm registers can be set at the same time to trigger alarms. The IRQ/FOUT output will be set by either alarm, and will need to be cleared to enable triggering by a subsequent alarm. Polling the SR will reveal which alarm has been set. 2. Interrupt Mode (or "Pulsed Interrupt Mode" or PIM) is enabled by setting the AL0E or AL1E bit to "1" the IM bit to "1", and disabling the frequency output. If both AL0E and AL1E bits are set to 1, then only the AL0E PIM alarm will function (AL0E overrides AL1E). The IRQ/FOUT output will now be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. Interrupt Mode CANNOT be used for general periodic alarms, however, since a specific time period cannot be programmed for interrupt, only matches to a specific time of day. The interrupt mode is only stopped by disabling the IM bit or the Alarm Enable bits. There are two options for setting the change-over conditions from VDD to Battery back-up mode. The BSW bit in the PWR register controls this operation. - Option 1 - Standard Mode - Option 2 - Legacy Mode (Default) Note that the I2C bus may or may not be operational during battery backup, that function is controlled by the SBIB bit. That operation is covered after the power control section. OPTION 1 - STANDARD POWER CONTROL MODE In the Standard mode, the supply will switch over to the battery when VDD drops below VTRIP or VBAT, whichever is lower. In this mode, accidental operation from the battery is prevented since the battery backup input will only be used when the VDD supply is shut off. To select Option 1, BSW bit in the Power Register must be set to "BSW = 0". A description of power switchover follows Standard Mode Power Switchover * Normal Operating Mode (VDD) to Battery Backup Mode (VBAT) To transition from the VDD to VBAT mode, both of the following conditions must be met: - Condition 1: VDD < VBAT - VBATHYS where VBATHYS 50mV - Condition 2: VDD < VTRIP where VTRIP 2.2V * Battery Backup Mode (VBAT) to Normal Mode (VDD) The ISL12028 device will switch from the VBAT to VDD mode when one of the following conditions occurs: - Condition 1: VDD > VBAT + VBATHYS where VBATHYS 50mV - Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS 30mV There are two discrete situations that are possible when using Standard Mode: VBAT< VTRIP and VBAT >VTRIP.
Power Control Operation
The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power an Intersil RTC device for up to 10 years. Another option is to use a SuperCap for applications where VDD is interrupted for up to a month. See the Applications Section for more information.
15
FN8233.3 April 17, 2006
ISL12028
These two power control situations are illustrated in Figures 13 and 14.
VBAT
Off
VDD
VOLTAGE On In
VDD
BATTERY BACKUP MODE
VTRIP VBAT VBAT - VBATHYS
2.2V 1.8V VBAT + VBATHYS
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
Power On Reset
Application of power to the ISL12028 activates a Power On Reset Circuit that pulls the RESET pin active. This signal provides several benefits. - It prevents the system microprocessor from starting to operate with insufficient voltage. - It prevents the processor from operating prior to stabilization of the oscillator. - It allows time for an FPGA to download its configuration prior to initialization of the circuit. - It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power up. When VDD exceeds the device VRESET threshold value for typically 250ms the circuit releases RESET, allowing the system to begin operation. Recommended slew rate is between 0.2V/ms and 50V/ms.
FIGURE 13. BATTERY SWITCHOVER WHEN VBAT < VTRIP
VDD VBAT VTRIP VTRIP
BATTERY BACKUP MODE
3.0V 2.2V VTRIP + VTRIPHYS
FIGURE 14. BATTERY SWITCHOVER WHEN VBAT > VTRIP
Watchdog Timer Operation
The watchdog timer timeout period is selectable. By writing a value to WD1 and WD0, the watchdog timer can be set to 3 different time out periods or off. When the Watchdog timer is set to off, the watchdog circuit is configured for low power operation. See Table 7.
TABLE 7. WD1 1 1 0 0 WD0 1 0 1 0 DURATION disabled 250ms 750ms 1.75s
OPTION 2 - LEGACY POWER CONTROL MODE (DEFAULT) The Legacy Mode follows conditions set in X1226 products. In this mode, switching from VDD to VBAT is simply done by comparing the voltages and the device operates from whichever is the higher voltage. To select the Option 2, BSW bit in the Power Register must be set to "BSW = 1" * Normal Mode (VDD) to Battery Backup Mode (VBAT) To transition from the VDD to VBAT mode, the following conditions must be met: VDD < VBAT - VBATHYS * Battery Backup Mode (VBAT) to Normal Mode (VDD) The device will switch from the VBAT to VDD mode when the following condition occurs: VDD > VBAT +VBATHYS The Legacy Mode power control conditions are illustrated in Figure 15.
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA when the SCL line is high (START condition). The start signal restarts the watchdog timer counter, resetting the period of the counter back to the maximum. If another START fails to be detected prior to the watchdog timer expiration, then the RESET pin becomes active for one reset time out period. In the event that the start signal occurs during a reset time out period, the start will have no effect. When using a single START to refresh watchdog timer, a STOP condition should be followed to reset the device back to stand-by mode. See Figure 3.
16
FN8233.3 April 17, 2006
ISL12028
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator compares the level of the VDD line versus a preset threshold voltage (VRESET), then generates a RESET pulse if it is below VRESET. The reset pulse will timeout 250ms after the VDD line rises above VRESET. If the VDD remains below VRESET, then the RESET output will remain asserted low. Power up and power down waveforms are shown in Figure 4. The LVR circuit is to be designed so the RESET signal is valid down to VDD = 1.0V. When the LVR signal is active, unless the part has been switched into the battery mode, the completion of an inprogress non-volatile write cycle is unaffected, allowing a non-volatile write to continue as long as possible (down to the Reset Valid Voltage). The LVR signal, when active, will terminate any in-progress communications to the device and prevents new commands from disrupting any current write operations. See "I2C Communications During Battery Backup and LVR Operation". STOP CONDITION All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 17. ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 18. The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will not acknowledge if the slave address byte is incorrect. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state.
Serial Communication
The device supports the I2C bidirectional serial bus protocol. CLOCK AND DATA Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. (See Figure 16.) START CONDITION All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 17.
SCL
SDA DATA STABLE DATA CHANGE DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
SCL
SDA START STOP
FIGURE 17. VALID START AND STOP CONDITIONS
17
FN8233.3 April 17, 2006
ISL12028
SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER
1
8
9
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
Device Addressing
Following a start condition, the master must output a Slave Address Byte. The first four bits of the Slave Address Byte specify access to either the EEPROM array or to the CCR. Slave bits `1010' access the EEPROM array. Slave bits `1101' access the CCR. When shipped from the factory, EEPROM array is UNDEFINED, and should be programmed by the customer to a known state. Bit 3 through Bit 1 of the slave byte specify the device select bits. These are set to `111'. The last bit of the Slave Address Byte defines the operation to be performed. When this R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 19. After loading the entire Slave Address Byte from the SDA bus, the ISL12028 compares the device identifier and device
DEVICE IDENTIFIER
select bits with `1010111' or `1101111'. Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a two byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power up the internal address counter is set to address 0h, so a current address read of the EEPROM array starts at address 0. When required, as part of a random read, the master must supply the 2 Word Address Bytes as shown in Figure 19. In a random read operation, the slave byte in the "dummy write" portion must match the slave byte in the "read" section. That is if the random read is from the array the slave byte must be 1010111x in both instances. Similarly, for a random read of the Clock/Control Registers, the slave byte must be 1101111x in both places.
Array CCR
1 1
0 1
1 0
0 1
1
1
1
R/W
SLAVE ADDRESS BYTE BYTE 0
0
0
0
0
0
0
0
A8
WORD ADDRESS 1 BYTE 1
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS 0 BYTE 2
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE BYTE 3
FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)
18
FN8233.3 April 17, 2006
ISL12028
Write Operations
BYTE WRITE For a write operation, the device requires the Slave Address Byte and the Word Address Bytes. This gives the master access to any one of the words in the array or CCR. (Note: Prior to writing to the CCR, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. See "Writing to the Clock/Control Registers.") Upon receipt of each address byte, the ISL12028 responds with an acknowledge. After receiving both address bytes the ISL12028 awaits the eight bits of data. After receiving the 8 data bits, the ISL12028 again responds with an acknowledge. The master then terminates the transfer by generating a stop condition. The ISL12028 then begins an internal write cycle of the data to the nonvolatile memory. During the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 20. A write to a protected block of memory is ignored, but will still receive an acknowledge. At the end of the write command, the ISL12028 will not initiate an internal write cycle, and will continue to ACK commands. PAGE WRITE The ISL12028 has a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 15 more bytes to the memory array and up to 7 more bytes to the clock/control registers. The RTC registers require a page write (8 bytes), individual register writes are not allowed. (Note: Prior to writing to the CCR, the master must write a 02h, then 06h to the status register in two preceding operations to enable the
S T A R T
write operation. See "Writing to the Clock/Control Registers.") After the receipt of each byte, the ISL12028 responds with an acknowledge, and the address is internally incremented by one.The address pointer remains at the last address byte written. When the counter reaches the end of the page, it "rolls over" and goes back to the first address on the same page. This means that the master can write 16 bytes to a memory array page or 8 bytes to a CCR section starting at any location on that page. For example, if the master begins writing at location 10 of the memory and loads 15 bytes, then the first 6 bytes are written to addresses 10 through 15, and the last 6 bytes are written to columns 0 through 5. Afterwards, the address counter would point to location 6 on the page that was just written. If the master supplies more than the maximum bytes in a page, then the previously loaded data is over-written by the new data, one byte at a time. Refer to Figure 21.The master terminates the Data Byte loading by issuing a stop condition, which causes the ISL12028 to begin the non-volatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 22 for the address, acknowledge, and data transfer sequence. STOPS AND WRITE MODES Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it's associated ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte + ACK is sent, then the ISL12028 resets itself without performing the write. The contents of the array are not affected.
.
SIGNALS FROM THE MASTER
SLAVE ADDRESS
WORD ADDRESS 1
WORD ADDRESS 0
DATA
S T O P
SDA BUS SIGNALS FROM THE SLAVE
1
1110 A C K
0000000
A C K A C K A C K
FIGURE 20. BYTE WRITE SEQUENCE
6 BYTES
6 BYTES
ADDRESS = 5 ADDRESS POINTER ENDS AT ADDR = 5
ADDRESS 10
ADDRESS 15
FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
19
FN8233.3 April 17, 2006
ISL12028
S T A R T 1 n 16 for EEPROM array 1 n 8 for CCR SLAVE ADDRESS WORD ADDRESS 1 WORD ADDRESS 0 DATA (1) DATA (n) S T O P
SIGNALS FROM THE MASTER
SDA BUS
1
11 10 A C K
000 00 00
A C K A C K A C K
SIGNALS FROM THE SLAVE
FIGURE 22. PAGE WRITE SEQUENCE
ACKNOWLEDGE POLLING Disabling of the inputs during non-volatile write cycles can be used to take advantage of the typical 5mS write cycle time. Once the stop condition is issued to indicate the end of the master's byte load operation, the ISL12028 initiates the internal non-volatile write cycle. Acknowledge polling can begin immediately. To do this, the master issues a start condition followed by the Memory Array Slave Address Byte for a write or read operation (AEh or AFh). If the ISL12028 is still busy with the non-volatile write cycle then no ACK will be returned. When the ISL12028 has completed the write operation, an ACK is returned and the host can proceed with the read or write operation. Refer to the flow chart in Figure 24. Note: Do not use the CCR Slave byte (DEh or DFh) for Acknowledge Polling. READ OPERATIONS There are three basic read operations: Current Address Read, Random Read, and Sequential Read.
condition. Refer to Figure 23 for the address, acknowledge, and data transfer sequence.
S T A R T S T O P
SIGNALS FROM THE MASTER
SLAVE ADDRESS
SDA BUS
1
1 1 11 A C K
SIGNALS FROM THE SLAVE
DATA
FIGURE 23. CURRENT ADDRESS READ SEQUENCE
Current Address Read
Internally the ISL12028 contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the sixteen bit address is initialized to 0h. In this way, a current address read immediately after the power on reset can download the entire contents of memory starting at the first location.Upon receipt of the Slave Address Byte with the R/W bit set to one, the ISL12028 issues an acknowledge, then transmits eight data bits. The master terminates the read operation by not responding with an acknowledge during the ninth clock and issuing a stop
20
FN8233.3 April 17, 2006
ISL12028
Byte with the R/W bit set to zero, the master must first perform a "dummy" write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. After acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit data word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 25 for the address, acknowledge, and data transfer sequence. In a similar operation called "Set Current Address," the device sets the address if a stop is issued instead of the second start shown in Figure 25. The ISL12028 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. SEQUENTIAL READ Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter "rolls over" to the start of the address space and the ISL12028 continues to output data for each acknowledge received. Refer to Figure 26 for the acknowledge and data transfer sequence.
Byte load completed by issuing STOP. Enter ACK Polling
Issue START
Issue Memory Array Slave Address Byte AFh (Read) or AEh (Write)
Issue STOP
ACK returned?
NO
YES nonvolatile write Cycle complete. Continue command sequence? NO Issue STOP
YES Continue normal Read or Write command sequence
PROCEED
FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. RANDOM READ Random read operations allow the master to access any location in the ISL12028. Prior to issuing the Slave Address
SIGNALS FROM THE MASTER
S T A R T
SLAVE ADDRESS
WORD ADDRESS 1
WORD ADDRESS 0
S T A R T
SLAVE ADDRESS
S T O P
SDA BUS
1
1 110 A C K
00 00000
A C K A C K
1
1 1 11 A C K
SIGNALS FROM THE SLAVE
DATA
FIGURE 25. RANDOM ADDRESS READ SEQUENCE
21
FN8233.3 April 17, 2006
ISL12028
SIGNALS FROM THE MASTER
SLAVE ADDRESS
A C K
A C K
A C K
S T O P
SDA BUS SIGNALS FROM THE SLAVE
1 A C K
DATA (1)
DATA (2)
DATA (n-1)
DATA (n)
(n is any integer greater than 1)
FIGURE 26. SEQUENTIAL READ SEQUENCE
Application Section
Crystal Oscillator and Temperature Compensation
Intersil has now integrated the oscillator compensation circuity on-chip, to eliminate the need for external components and adjust for crystal drift over temperature and enable very high accuracy time keeping (<5ppm drift). The Intersil RTC family uses an oscillator circuit with on-chip crystal compensation network, including adjustable loadcapacitance. The only external component required is the crystal. The compensation network is optimized for operation with certain crystal parameters which are common in many of the surface mount or tuning-fork crystals available today. Table 8 summarizes these parameters. Table 9 contains some crystal manufacturers and part numbers that meet the requirements for the Intersil RTC products. The turnover temperature in Table 8 describes the temperature where the apex of the of the drift vs. temperature curve occurs. This curve is parabolic with the drift increasing as (T-T0)2. For an Epson MC-405 device, for example, the turnover temperature is typically 25C, and a peak drift of >110ppm occurs at the temperature extremes of
-40 and +85C. It is possible to address this variable drift by adjusting the load capacitance of the crystal, which will result in predictable change to the crystal frequency. The Intersil RTC family allows this adjustment over temperature since the devices include on-chip load capacitor trimming. This control is handled by the Analog Trimming Register, or ATR, which has 6 bits of control. The load capacitance range covered by the ATR circuit is approximately 3.25pF to 18.75pF, in 0.25pF increments. Note that actual capacitance would also include about 2pF of package related capacitance. In-circuit tests with commercially available crystals demonstrate that this range of capacitance allows frequency control from +116ppm to -37ppm, using a 12.5pF load crystal. In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are three bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is 30ppm in increments of 10ppm. The default setting is 0ppm. The DTR control can be used for coarse adjustments of frequency drift over temperature or for crystal initial accuracy correction.
TABLE 8. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC PARAMETER Frequency Frequency Tolerance Turnover Temperature Operating Temperature Range Parallel Load Capacitance Equivalent Series Resistance 20 -40 12.5 50 25 MIN TYP 32.768 100 30 85 MAX UNITS kHz ppm C C pF k For best oscillator performance Down to 20ppm if desired Typically the value used for most crystals NOTES
22
FN8233.3 April 17, 2006
ISL12028
TABLE 9. CRYSTAL MANUFACTURERS MANUFACTURER Citizen Epson Raltron SaRonix Ecliptek ECS Fox PART NUMBER CM201, CM202, CM200S MC-405, MC-406 RSM-200S-A or B 32S12A or B ECPSM29T-32.768K ECX-306/ECX-306I FSM-327 TEMP RANGE -40 to +85C -40 to +85C -40 to +85C -40 to +85C -10 to +60C -10 to +60C -40 to +85C +25C FREQUENCY TOLERANCE 20ppm 20ppm 20ppm 20ppm 20ppm 20ppm 20ppm
A final application for the ATR control is in-circuit calibration for high accuracy applications, along with a temperature sensor chip. Once the RTC circuit is powered up with battery backup, the IRQ/FOUT output is set at 32.768kHz and frequency drift is measured. The ATR control is then adjusted to a setting which minimizes drift. Once adjusted at a particular temperature, it is possible to adjust at other discrete temperatures for minimal overall drift, and store the resulting settings in the EEPROM. Extremely low overall temperature drift is possible with this method. The Intersil evaluation board contains the circuitry necessary to implement this control. For more detailed operation see Intersil's application note AN154 on Intersil's website at www.intersil.com.
The X1 and X2 connections to the crystal are to be kept as short as possible. A thick ground trace around the crystal is advised to minimize noise intrusion, but ground near the X1 and X2 pins should be avoided as it will add to the load capacitance at those pins. Keep in mind these guidelines for other PCB layers in the vicinity of the RTC device. A small decoupling capacitor at the VDD pin of the chip is mandatory, with a solid connection to ground. For other RTC products, the same rules stated above should be observed, but adjusted slightly since the packages and pinouts are slightly different.
Layout Considerations
The crystal input at X1 has a very high impedance and will pick up high frequency signals from other circuits on the board. Since the X2 pin is tied to the other side of the crystal, it is also a sensitive node. These signals can couple into the oscillator circuit and produce double clocking or misclocking, seriously affecting the accuracy of the RTC. Care needs to be taken in layout of the RTC circuit to avoid noise pickup. Below in Figure 27 is a suggested layout for the ISL12029 or ISL12028 devices.
C1 0.1F
XTAL1 32.768kHz 32.768kGz
R1 10k U1 ISL12028 X1228
FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-14
23
FN8233.3 April 17, 2006
ISL12028
Oscillator Measurements
When a proper crystal is selected and the layout guidelines above are observed, the oscillator should start up in most circuits in less than one second. Some circuits may take slightly longer, but startup should definitely occur in less than 5 seconds. When testing RTC circuits, the most common impulse is to apply a scope probe to the circuit at the X2 pin (oscillator output) and observe the waveform. DO NOT DO THIS! Although in some cases you may see a usable waveform, due to the parasitics (usually 10pF to ground) applied with the scope probe, there will be no useful information in that waveform other than the fact that the circuit is oscillating. The X2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected by the parasitic elements in the scope probe. Applying a scope probe can possibly cause a faulty oscillator to start up, hiding other issues (although in the Intersil RTC's, the internal circuitry assures startup when using the proper crystal and layout). The best way to analyze the RTC circuit is to power it up and read the real time clock as time advances, or if the chip has the IRQ/FOUT output, look at the output of that pin on an oscilloscope (after enabling it with the control register, and using a pull-up resistor for the open-drain output). Alternatively, the ISL12028 IRQ/FOUT- output can be checked by setting an alarm for each minute. Using the pulse interrupt mode setting, the once-per-minute interrupt functions as an indication of proper oscillation. and backup time is reduced. In this case if alarms are used in backup mode, the IRQ/FOUT pull up resistor must be connected to VBAT voltage source. During initial power up the default mode is the Standard mode.
2.7-5.5V
VCC
Vback Supercapacitor VSS
FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT
I2C Communications During Battery backup and LVR Operation
Operation in Battery Backup mode and LVR is affected by the BSW and SBIB bits as described earlier. These bits allow flexible operation of the serial bus and EEPROM in battery backup mode, but certain operational details need to be clear before utilizing the different modes. The most significant detail is that once VDD goes below VRESET, then I2C communications cease regardless of whether the device is programmed for I2C operation in battery backup mode. Table 10 describes 4 different modes possible with using the BSW and SBIB bits, and how they are affect LVR and battery backup operation. * Mode A - In this mode selection bits indicate a low VDD switchover combined with I2C operation in battery backup mode. In actuality the VDD will go below VRESET before switching to battery backup, which will disable I2C ANYTIME the device goes into battery backup mode. Regardless of the battery voltage, the I2C will work down to the VRESET voltage. See Figure 29.
Backup Battery Operation
Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for up to 10 years. Another option is to use a supercapacitor for applications where VDD may disappear intermittently for short periods of time. Depending on the value of supercapacitor used, backup time can last from a few days to two weeks (with >1F). A simple silicon or Schottky barrier diode can be used in series with VDD to charge the supercapacitor, which is connected to the VBAT pin. Try to use Schottky diodes with very low leakages, <1A desirable. Do not use the diode to charge a battery (especially lithium batteries!). There are two possible modes for battery backup operation, Standard and Legacy mode. In Standard mode, there are no operational concerns when switching over to battery backup since all other devices functions are disabled. Battery drain is minimal in Standard mode, and return to Normal VDD powered operations predictable. In Legacy modes the VBAT pin can power the chip if the voltage is above VDD and VTRIP. This makes it possible to generate alarms and communicate with the device under battery backup, but the supply current drain is much higher than the Standard mode
24
FN8233.3 April 17, 2006
ISL12028
TABLE 10. I2C, LV RESET, AND BATTERY BACKUP OPERATION SUMMARY (SHADED ROW IS SAME AS X1228 OPERATION) SBIB BIT 0 BSW BIT 0 VBAT SWITCHOVER VOLTAGE Standard Mode, VTRIP = 2.2V typ I2C ACTIVE IN BATTERY BACKUP? NO EE PROM WRITE/ READ IN BATTERY BACKUP? NO FREQ/IRQ ACTIVE? YES
2
MODE A
NOTES Operation of I C bus down to VDD = VRESET, then below that no communications. Battery switchover at VTRIP. Operation of I2C bus into battery backup mode, but only for VBAT>VDD>VRESET. Bus must have pullups to VBAT. Operation of I2C bus down to VDD = VRESET, then below that no communications. Battery switchover at VTRIP. Operation of I2C busdown to VRESET or VBAT, whichever is higher.
B (X1228 mode) C
0
1
Legacy Mode, VDD < VBAT
YES, only if VBAT>VRESET
YES
YES
1
0
Standard Mode, VTRIP = 2.2V typ
NO
NO
YES
D
1
1
Legacy Mode, VDD < VBAT
NO
NO
YES
* Mode B - In this mode the selection bits indicate switchover to battery backup at VDD* Mode D - In this mode the selection bits indicate switchover to battery backup at VDDISL12028 device which has an open-drain output and avoids excessive current draw in battery backup.
VDD
VBAT(3.0V) VRESET(2.63V) VTRIP (2.2V)
tPURST
RESET
I2C Bus Active
IBAT
(VDD power, VBAT not connected)
(Battery backup mode)
FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C
25
FN8233.3 April 17, 2006
ISL12028
VDD
VBAT(3.0V) VRESET(2.63V) VTRIP (2.2V)
tPURST
RESET I2C Bus Active
IBAT
(Battery backup mode)
FIGURE 30. RESET OPERATION IN MODE D
Alarm Operation Examples
Below are examples of both Single Event and periodic Interrupt Mode alarms. Example 1 - Alarm 0 set with single interrupt (IM = "0") A single alarm will occur on January 1 at 11:30am. A. Set Alarm 0 registers as follows:
ALARM0 REGISTER 7 SCA0 MNA0 HRA0 DTA0 MOA0 DWA0 0 1 1 1 1 0 BIT 6 0 0 0 0 0 0 5 0 1 0 0 0 0 4 0 1 1 0 0 0 3 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 HEX DESCRIPTION
Example 2 - Pulsed interrupt once per minute (IM = "1") Interrupts at one minute intervals when the seconds register is at 30 seconds. A. Set Alarm 0 registers as follows:
BIT ALARM0 REGISTER 7 6 5 4 3 2 1 0 HEX SCA0 MNA0 HRA0 DTA0 MOA0 DWA0
DESCRIPTION
1 0 1 1 0 0 0 0 B0h Seconds set to 30, enabled 0 0 0 0 0 0 0 0 00h Minutes disabled 0 0 0 0 0 0 0 0 00h Hours disabled 0 0 0 0 0 0 0 0 00h Date disabled 0 0 0 0 0 0 0 0 00h Month disabled 0 0 0 0 0 0 0 0 00h Day of week disabled
00h Seconds disabled B0h Minutes set to 30, enabled 91h Hours set to 11, enabled 81h Date set to 1, enabled 81h Month set to 1, enabled 00h Day of week disabled
B. Set the Interrupt register as follows:
BIT CONTROL REGISTER 7 6 5 4 3 2 1 0 HEX INT
DESCRIPTION
1 0 1 x x 0 0 0 x0h Enable Alarm and Int Mode
B. Also the AL0E bit must be set as follows:
CONTROL REGISTER 7 INT 0 BIT 6 0 5 1 4 0 3 0 2 0 1 0 0 0 HEX x0h DESCRIPTION Enable Alarm
XX indicate other control bits. Once the registers are set, the following waveform will be seen at IRQ/FOUT-:
RTC and alarm registers are both "30" sec
After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the AL0 bit in the status register to "1" and also bringing the IRQ/FOUT output low.
60 sec
Note that the status register AL0 bit will be set each time the alarm is triggered, but does not need to be read or cleared.
26
FN8233.3 April 17, 2006
ISL12028 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574
A1 B C D E
A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
27
FN8233.3 April 17, 2006
ISL12028 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 MAX 0.047 0.006 0.051 0.0118 0.0079 0.199 0.177 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 NOTES 9 3 4 6 7 8o Rev. 1 6/00
A1 0.10(0.004) A2 c
e
b 0.10(0.004) M C AM BS
E1 e E L N
0.026 BSC 0.246 0.0177 14 0o 8o 0.256 0.0295
0.65 BSC 6.25 0.45 14 0o 6.50 0.75
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 28
FN8233.3 April 17, 2006

▲Up To Search▲

Price & Availability of ISL12028

	To Download ISL12028 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .